Field of the Invention
The present invention relates to a control circuit of a plurality of Schottky Transistor Logic (STL) type logic cells in parallel.
A STL type logic cell is shown in FIG. 1. It comprises a NPN transistor T, a Schottky diode of a first type SP connected in parallel with the base-collector junction of the transistor, conductive from the base towards the collector, Schottky diodes of a second type ST1 to ST4 conductive between the output terminals S1 to S4 and the collector of transistor T, and a resistance R connecting the base of the transistor T, which is also connected to an input terminal E, at a supply voltage VCC. The emitter of the transistor T is connected to the ground.
This kind of cell can occupy a very small surface area on an integrated circuit since the all of the components T, SP and ST1 to ST4 can be integrated inside a single well without intervening insulating walls. The SP and ST Schottky diodes are such that the direct voltage drop (VSP) in the diode SP is greater than the direct voltage drop (VST) in a ST diode. The SP diode is, for example, an N type platinum silicide/silicon Schottky diode of which the direct voltage drop is about 620 mV at 25.degree. C. and the ST diodes are N type titanium/silicon Schottky diodes in which the direct voltage drop is about 420 mV at 25.degree. C., i.e. VSP-VST=200 mV. In theory, this difference in voltage slightly varies with the temperature.
This logic cell constitutes an inverter able to assume either of two states: low input/high outputs or high input/low outputs.
In order to examine the threshold voltage of this kind of cell, it will be presumed that the input is connected to an output of a preceding cell and that the outputs are connected to the inputs of following cells. In the high state of a cell (low input/high outputs), the transistor of this cell is blocked while the transistors of the preceding and following cells are conductive. The output terminals of the cell are thus at a voltage VS(1) that corresponds to the base-emitter voltage of a conductive transistor, in other terms VS(1)=VBE. The input terminal is at a voltage VE(0)=VBE-VSP+VST, or in the numerical example indicated above VBE-0.2 V. In the low state (the transistor of the cell involved being conductive) the input and output voltages are inverted, i.e. VE(1)=VBE and VS(0)=VBE-VSP+VST.
It will be noted that the difference of potential between the high and the low states is relatively small in this type of logic circuit, typically about 0.2 V.
The output capacity of a STL cell will now be considered, i.e. the number of output terminals that can be associated with this kind of cell (4 in the example of FIG. 1A), while maintaining satisfactory operation. At the low state of the output, the transistor T is conductive and the current in this transistor depends upon the number n of output terminals associated with the cell. In fact, it should be recalled that each output terminal is connected to a supply voltage source VCC through the intermediary of a resistor R of the following cell. If the number of output terminals is equal to n, the current flowing through the transistor is substantially equal to (n/1) (VCC-VBE)/R. It is known that when the collector-emitter current in a transistor increases, this results in an increase of the base-emitter voltage drop VBE of this transistor. Therefore, the high and low levels of the transistor move closer together since, as previously seen, for the high state VS(1)=VBE1 and for the low state VS(0)=VBE2-VSP+VST with VBE2 greater that VBE1. Furthermore, an increase of the base-emitter voltage corresponds to an increase in the base current and consequently a reduction of current in the Schottky diode SP. As a result the drop in voltage in this Schottky diode decreases, thereby further contributing to the increase in threshold voltage at the low state VS(0) which moves close to VS(1). Consequently, the high and low states of the logic circuit become difficult to differentiate. Practical calculations show that in fact the output capacity of a STL cell is limited to a value of about 4, i.e. it is not possible to connect more than four Schottky diodes ST in parallel at the output.
Consequently, if it is desired to control n cells where n is greater than four with a single signal, due to the output capacity being limited to 4 per cell unit, it is necessary to provide a control cell CA, equivalent to n/4 elementary cells in parallel. In practice, this is performed by multiplying by the factor n/4 the surface of the transistor T and of the diode SP, and by dividing by the same factor the value of the resistor R. In order to avoid n connections towards the n controlled cells Cl to Cn, the n output diodes STAl to STAn of the cell CA are moved to locations close to the input terminal of the controlled cells. Thus, a single connection distributes the control signal. This is the solution proposed by the prior art represented in FIG. 1B.
An alternative solution consisting of connecting, on the control connection, the n inputs of the controlled cells is not applicable for various reasons. In particular, all the base-emitter junctions of the cells to be controlled are in parallel and, if a small shift or difference exists between the base-emitter voltages of these cells due, for example, to a lack of similarity in the transistors of the integrated circuits, to an impedance difference of the emitter-ground connection, or to a different value of the current, this will result in certain cells no longer ensuring the logic zero at their output. These various reasons are summarily designated in the literature under the name of "Hogging effect".
The drawbacks of the prior art set out above are the following:
to ensure the logic zero, the control cell must absorb the n currents of the cells controlled through a relatively long connection (n=about 200 to 1,000), this connection must also be very large in order to limit the voltage drop that is to be deducted from the logic jump (which is already small per se) of the STL logic, thereby causing a loss of space and a high stray capacity.
the displaced diodes ST must have their individual insulating wells, which also involves a loss of space and a very high stray capacitance (n times the well/substrate capacitance) on the control line.
The total stray capacitance (metallization and diodes) on the line can only be compensated (in the worst case where n-1 inputs are at logic zero) by the single elementary current of the cell unit of which the input is a logic 1, which results in a considerable delay in the transistion 0/1.
in the worst case where n-1 inputs are at state 0, the inverse leak current of the displaced n-1 diodes is deducted from the useful current of the single input at the state 1. The diodes ST having a low threshold, the inverse currents are particularly strong at 150.degree. C.
the input current of the control cell being one quarter of the output current, which is n times the elementary current, it is necessary to provide several control cells in cascade, before assuring the control by a single elementary cell, which results in a loss of space, an increase in consumption and an increase in propagation time.
The drawbacks mentioned herein-above render very difficult, or even impossible the direct control in parallel of a large number of STL gates (200 to 1,000) by this method. In certain logic structures, for example of the pipe line type, that are increasingly utilized, the parallelism of the calculation involves the parallelism of the sequency controls thereby requiring control of a great number of logic gates by a single signal (for example by a register clock-signal).
One object of the present invention is to achieve this result in a simple manner, while utilizing an integrated circuit having a small surface area.
With this purpose in view, the present invention provides a control circuit of a great number of STL logic cells in parallel. These cells each comprise a transistor, a first Schottky diode connected between the base and the collector of this transistor, a plurality of second Schottky diodes connected to the collector of this transistor, an input terminal connected to the base of the transistor, output terminals connected to the second Schottky diodes, a power supply terminal connected to the base of the transistor through a resistor and a ground terminal connected to the emitter of the transistor. In this circuit, the power supply terminals of the cells in parallel are connected to the power supply source through switching means controlled by the logic signal that is to be applied to the said cells, the input terminals of the said cells being connected to the output terminals of other STL cells.
In one embodiment of the present invention, the switching means, in a first state, supply the standard supply voltage required for the STL cells and, in a second state, supply a voltage close to the level of the ground.
In another embodiment of the invention, the switching means are connected to the standard power supply source and comprise a second higher voltage source and means to supply, in the first state, exactly the voltage of the standardized voltage source through compensation of the voltage drops of the transistors of the circuit.
In one embodiment of the present invention, the commutation means comprise:
at least one input Schottky diode;
a first input Schottky transistor;
a second Schottky transistor the base of which is connected to the emitter of the first Schottky transistor, the emitter of which is connected to the ground while its collector is connected to an output terminal, and
two transistors forming a Darlington circuit between the second power source and the said output terminal, the base of the first of these transistors being connected:
to the collector of the first Schottky transistor, PA1 to the second power source through a biasing resistor; and PA1 to the first power source supplying the standardized power voltage, through two diodes.